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INTEGRATED CIRCUITS
DATA SHEET
UDA1334BT Low power audio DAC
Product specification 2002 May 22
Philips Semiconductors
Product specification
Low power audio DAC
CONTENTS 1 1.1 1.2 1.3 1.4 2 3 4 5 6 7 8 8.1 8.2 8.3 8.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 9 10 11 12 FEATURES General Multiple format data interface DAC digital sound processing Advanced audio configuration APPLICATIONS GENERAL DESCRIPTION ORDERING INFORMATION QUICK REFERENCE DATA BLOCK DIAGRAM PINNING FUNCTIONAL DESCRIPTION System clock Interpolation filter Noise shaper Filter stream DAC Power-on reset Feature settings Digital interface format select Mute control De-emphasis control Power control and sampling frequency select LIMITING VALUES HANDLING THERMAL CHARACTERISTICS QUALITY SPECIFICATION 13 14 14.1 14.2 14.3 15 16 17 17.1 17.2 17.3 17.4 17.5 18 19 20
UDA1334BT
DC CHARACTERISTICS AC CHARACTERISTICS 2.0 V supply voltage 3.0 V supply voltage Timing APPLICATION INFORMATION PACKAGE OUTLINE SOLDERING Introduction to soldering surface mount packages Reflow soldering Wave soldering Manual soldering Suitability of surface mount IC packages for wave and reflow soldering methods DATA SHEET STATUS DEFINITIONS DISCLAIMERS
2002 May 22
2
Philips Semiconductors
Product specification
Low power audio DAC
1 1.1 FEATURES General
UDA1334BT
* 1.8 to 3.6 V power supply voltage * Integrated digital filter plus DAC * Supports sample frequencies from 8 to 100 kHz * Automatic system clock versus sample rate detection * Low power consumption * No analog post filtering required for DAC * Slave mode only applications * Easy application * SO16 package. 1.2 Multiple format data interface 2 APPLICATIONS
This audio DAC is excellently suitable for digital audio portable application, such as portable MD, MP3 and DVD players. 3 GENERAL DESCRIPTION
* I2S-bus and LSB-justified format compatible * 1fs input data rate. 1.3 DAC digital sound processing
The UDA1334BT supports the I2S-bus data format with word lengths of up to 24 bits and the LSB-justified serial data format with word lengths of 16, 20 and 24 bits. The UDA1334BT has basic features such as de-emphasis (at 44.1 kHz sampling rate) and mute.
* Digital de-emphasis for 44.1 kHz sampling rate * Mute function. 1.4 Advanced audio configuration
* High linearity, wide dynamic range and low distortion * Standby or Sleep mode in which the DAC is powered down. 4 ORDERING INFORMATION TYPE NUMBER UDA1334BT PACKAGE NAME SO16 DESCRIPTION plastic small outline package; 16 leads; body width 3.9 mm VERSION SOT109-1
2002 May 22
3
Philips Semiconductors
Product specification
Low power audio DAC
5 QUICK REFERENCE DATA SYMBOL Supplies VDDA VDDD IDDA IDDD DAC analog supply voltage digital supply voltage DAC analog supply current digital supply current normal operating mode Sleep mode normal operating mode Sleep mode clock running no clock running Tamb ambient temperature Digital-to-analog converter (VDDA = VDDD = 2.0 V) Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 fs = 44.1 kHz; at 0 dB fs = 44.1 kHz; at -60 dB; A-weighted fs = 96 kHz; at 0 dB fs = 96 kHz; at -60 dB; A-weighted S/N cs signal-to-noise ratio channel separation fs = 44.1 kHz; code = 0; A-weighted fs = 96 kHz; code = 0; A-weighted Digital-to-analog converter (VDDA = VDDD = 3.0 V) Vo(rms) output voltage (RMS value) at 0 dB (FS) digital input; note 1 fs = 44.1 kHz; at 0 dB fs = 44.1 kHz; at -60 dB; A-weighted fs = 96 kHz; at 0 dB fs = 96 kHz; at -60 dB; A-weighted S/N cs signal-to-noise ratio channel separation fs = 44.1 kHz; code = 0; A-weighted fs = 96 kHz; code = 0; A-weighted Power dissipation (at fs = 44.1 kHz) P power dissipation playback mode at 2.0 V supply voltage at 3.0 V supply voltage Sleep mode; at 2.0 V supply voltage clock running no clock running Note 1. The DAC output voltage scales proportionally to the power supply voltage. - - - - - - - - - - - - - - - - - - - - - - -40 1.8 1.8 - - - PARAMETER CONDITIONS MIN.
UDA1334BT
TYP.
MAX. UNIT
2.0 2.0 2.3 125 1.4 250 20 -
3.6 3.6 - - - - - +85 - - - - - - - - - - - - - - - -
V V mA A mA A A C
600 -80 -37 -75 -35 97 95 100
mV dB dB dB dB dB dB dB
(THD + N)/S total harmonic distortion-plus-noise to signal ratio
900 -90 -40 -85 -37 100 98 100
mV dB dB dB dB dB dB dB
(THD + N)/S total harmonic distortion-plus-noise to signal ratio
7.4 17 0.75 0.3
- - - -
mW mW mW mW
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
6 BLOCK DIAGRAM
UDA1334BT
handbook, full pagewidth
VDDD 4 1 2 3
VSSD 5
BCK WS DATAI
DIGITAL INTERFACE
UDA1334BT
SYSCLK MUTE DEEM PCS 6 8 9 10
DE-EMPHASIS 7 INTERPOLATION FILTER 11 SFOR1 SFOR0
NOISE SHAPER
VOUTL
14
DAC
DAC
16
VOUTR
13 VDDA
15 VSSA
12 Vref(DAC)
MGU676
Fig.1 Block diagram.
2002 May 22
5
Philips Semiconductors
Product specification
Low power audio DAC
7 PINNING PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 PAD TYPE 5 V tolerant digital input pad; note 1 5 V tolerant digital input pad; note 1 5 V tolerant digital input pad; note 1 digital supply pad digital ground pad 5 V tolerant digital input pad; note 1 5 V tolerant digital input pad; note 1 5 V tolerant digital input pad; note 1 5 V tolerant digital input pad; note 1 3-level input pad; note 2 digital input pad; note 2 analog pad analog supply pad analog output pad analog ground pad analog output pad bit clock input word select input serial data input digital supply voltage digital ground system clock input serial format select 1 mute control de-emphasis control
UDA1334BT
SYMBOL BCK WS DATAI VDDD VSSD SYSCLK SFOR1 MUTE DEEM PCS SFOR0 Vref(DAC) VDDA VOUTL VSSA VOUTR Notes
DESCRIPTION
power control and sampling frequency select serial format select 0 DAC reference voltage DAC analog supply voltage DAC output left DAC analog ground DAC output right
1. 5 V tolerant is only supported if the power supply voltage is between 2.7 and 3.6 V. For lower power supply voltages this is maximum 3.3 V tolerant. 2. Because of test issues these pads are not 5 V tolerant and they should be at power supply voltage level or at a maximum of 0.5 V above that level.
handbook, halfpage
BCK 1 WS 2 DATAI 3 VDDD 4 VSSD 5 SYSCLK 6 SFOR1 7 MUTE 8
MGU675
16 VOUTR 15 VSSA 14 VOUTL 13 VDDA 12 Vref(DAC) 11 SFOR0 10 PCS 9 DEEM
UDA1334BT
Fig.2 Pin configuration.
2002 May 22
6
Philips Semiconductors
Product specification
Low power audio DAC
8 8.1 FUNCTIONAL DESCRIPTION System clock Table 2
UDA1334BT
Example using a 12.228 MHz system clock SAMPLING FREQUENCY 96 kHz 64 kHz(1) 48 kHz 32 kHz 24 kHz 16 kHz
CLOCK MODE 128fs 192fs 256fs 384fs 512fs 768fs Note
The UDA1334BT operates in slave mode only; this means that in all applications the system must provide the system clock and the digital audio interface signals (BCK and WS). The system clock must be locked in frequency to the digital interface signals. The UDA1334BT automatically detects the ratio between the SYSCLK and WS frequencies. The BCK clock can be up to 64fs, or in other words the BCK frequency is 64 times the Word Select (WS) frequency or less: fBCK 64 x fWS. Remarks: 1. The WS edge MUST fall on the negative edge of the BCK at all times for proper operation of the digital I/O data interface 2. For LSB-justified formats it is important to have a WS signal with a duty factor of 50%. The modes which are supported are given in Table 1. Table 1 Supported sampling ranges SAMPLING RANGE 8 to 55 kHz 8 to 100 kHz 8 to 100 kHz 8 to 100 kHz 8 to 100 kHz(1)(2) 8 to 100 kHz(2) 8.3 8.2
1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192fs mode the sampling frequency should be limited to 55 kHz. Interpolation filter
The interpolation digital filter interpolates from 1fs to 64fs by cascading FIR filters (see Table 3). Table 3 Interpolation filter characteristics CONDITION 0 to 0.45fs >0.55fs 0 to 0.45fs VALUE (dB) 0.02 -50 >114
ITEM Pass-band ripple Stop band Dynamic range Noise shaper
CLOCK MODE 768fs 512fs 384fs 256fs 192fs 128fs Notes
The 5th-order noise shaper operates at 64fs. It shifts in-band quantization noise to frequencies well above the audio band. This noise shaping technique enables high signal-to-noise ratios to be achieved. The noise shaper output is converted into an analog signal using a Filter Stream DAC (FSDAC).
1. This mode can only be supported for power supply voltages down to 2.4 V. For lower voltages, in 192fs mode the sampling frequency should be limited to 55 kHz. 2. Not supported in the low sampling frequency mode. An example is given in Table 2 for a 12.228 MHz system clock input.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
8.4 Filter stream DAC 8.5 Power-on reset
UDA1334BT
The FSDAC is a semi-digital reconstruction filter that converts the 1-bit data stream of the noise shaper to an analog output voltage. The filter coefficients are implemented as current sources and are summed at virtual ground of the output operational amplifier. In this way very high signal-to-noise performance and low clock jitter sensitivity is achieved. No post-filter is needed due to the inherent filter function of the DAC. On-board amplifiers convert the FSDAC output current to an output voltage signal capable of driving a line output. The output voltage of the FSDAC scales proportionally with the power supply voltage.
The UDA1334BT has an internal Power-on reset circuit (see Fig.3) which resets the test control block. The reset time (see Fig.4) is determined by an external capacitor which is connected between pin Vref(DAC) and ground. The reset time should be at least 1 s for Vref(DAC) < 1.25 V. When VDDA is switched off, the device will be reset again for Vref(DAC) < 0.75 V. During the reset time the system clock should be running.
handbook, halfpage
3.0 VDDD (V) 1.5
0 t
handbook, halfpage
3.0 V
VDDA 13 50 k
3.0 VDDA (V) RESET CIRCUIT 50 k 1.5
Vref(DAC) C1 > 10 F
12
0 t 3.0 Vref(DAC) (V) 1.5
1.25 0.75
UDA1334BT
MGU678
0 >1 s t
MGL984
Fig.3 Power-on reset circuit.
Fig.4 Power-on reset timing.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
8.6 Feature settings 8.6.4
UDA1334BT
POWER CONTROL AND SAMPLING FREQUENCY
SELECT
The features of the UDA1334BT can be set by control pins SFOR1, SFOR0, MUTE, DEEM and PCS. 8.6.1 DIGITAL INTERFACE FORMAT SELECT
Pin PCS is a 3-level pin and is used to set the mode of the UDA1334BT. The definition is given in Table 7. Table 7 PCS LOW MID HIGH PCS function definition FUNCTION normal operating mode low sampling frequency mode Power-down or Sleep mode
The digital audio interface formats (see Fig.5) can be selected via the pins SFOR1 and SFOR0 as shown in Table 4. Table 4 Data format selection SFOR0 LOW HIGH LOW HIGH INPUT FORMAT I2S-bus input LSB-justified 16 bits input LSB-justified 20 bits input LSB-justified 24 bits input
SFOR1 LOW LOW HIGH HIGH 8.6.2
The low sampling frequency mode is required to have a higher oversampling rate in the noise shaper in order to improve the signal-to-noise ratio. In this mode the oversampling ratio of the noise shaper will be 128fs instead of 64fs.
MUTE CONTROL
The output signal can be soft muted by setting pin MUTE to HIGH level as shown in Table 5. Table 5 Mute control FUNCTION mute off mute on
MUTE LOW HIGH 8.6.3
DE-EMPHASIS CONTROL
De-emphasis can be switched on for fs = 44.1 kHz by setting pin DEEM at HIGH level. The function description of pin DEEM is given in Table 6. Table 6 De-emphasis control FUNCTION de-emphasis off de-emphasis on
DEEM LOW HIGH
Remark: the de-emphasis function in only supported in the normal operating mode, not in the low sampling frequency mode.
2002 May 22
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WS 1 BCK 2 3 LEFT >=8 1 2 3 RIGHT >=8 DATA MSB B2 MSB B2 I2S-BUS FORMAT WS LEFT 16 BCK 15 2 1 DATA MSB B2 B15 LSB LSB-JUSTIFIED FORMAT 16 BITS
Philips Semiconductors
handbook, full pagewidth
MSB RIGHT 16 15 2 1 MSB B2 B15 LSB
Low power audio DAC
10
WS LEFT 20 BCK 19 18 17 16 15 2 1 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B19 LSB LSB-JUSTIFIED FORMAT 20 BITS MSB B2 B3 B4 B5 B6 B19 LSB WS 24 BCK 23 22 21 LEFT 20 19 18 17 16 15 2 1 24 23 22 21 RIGHT 20 19 18 17 16 15 2 1 DATA MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB LSB-JUSTIFIED FORMAT 24 BITS MSB B2 B3 B4 B5 B6 B7 B8 B9 B10 B23 LSB
MGS752
UDA1334BT
Product specification
Fig.5 Digital audio formats
Philips Semiconductors
Product specification
Low power audio DAC
9 LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Txtal(max) Tstg Tamb Ves Isc(DAC) PARAMETER supply voltage maximum crystal temperature storage temperature ambient temperature electrostatic handling voltage short-circuit current of DAC human body model machine model note 2 output short-circuited to VSSA output short-circuited to VDDA Note 1. All supply connections must be made to the same power supply. - - note 1 CONDITIONS - - -65 -40 -2000 -200 MIN.
UDA1334BT
MAX. 4.0 150 +125 +85 +2000 +200 450 300 V
UNIT C C C V V mA mA
2. Short-circuit test at Tamb = 0 C and VDDA = 3 V. DAC operation after short-circuiting cannot be warranted. 10 HANDLING Inputs and outputs are protected against electrostatic discharge in normal handling. However, it is good practice to take normal precautions appropriate to handling MOS devices. 11 THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER CONDITIONS VALUE 145 UNIT K/W
thermal resistance from junction to ambient in free air
12 QUALITY SPECIFICATION In accordance with "SNW-FQ-611-D". 13 DC CHARACTERISTICS VDDD = VDDA = 2.0 V; Tamb = 25 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL Supplies VDDA VDDD IDDA DAC analog supply voltage note 1 digital supply voltage note 1 at 2.0 V supply voltage at 3.0 V supply voltage Sleep mode at 2.0 V supply voltage at 3.0 V supply voltage - - 125 175 - - A A DAC analog supply current normal operating mode - - 2.3 3.5 - - mA mA 1.8 1.8 2.0 2.0 3.6 3.6 V V PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
SYMBOL IDDD
PARAMETER digital supply current
CONDITIONS normal operating mode at 2.0 V supply voltage at 3.0 V supply voltage Sleep mode; at 2.0 V supply voltage clock running no clock running Sleep mode; at 3.0 V supply voltage clock running no clock running - - 1.3 2.0 - - - -
MIN. 1.4 2.1
TYP. - -
MAX.
UNIT mA mA
250 20
- -
A A
375 30 - - - - - - - - - 0.5VDDA 25 1.6 - -
- - 3.3 5.0 +0.5 +0.8 1 10
A A V V V V A pF
Digital input pins; note 2 VIH VIL ILI Ci VIH VIM VIL DAC Vref(DAC) Ro(ref) Io(max) RL CL Notes 1. All supply connections must be made to the same external power supply unit. 2. At 3 V supply voltage, the input pads are TTL compatible. However, at 2.0 V supply voltage no TTL levels can be accepted, but levels from 3.3 V domain can be applied to the pins. 3. When the DAC drives a capacitive load above 50 pF, a series resistance of 100 must be used to prevent oscillations in the output operational amplifier. reference voltage output resistance on pin Vref(DAC) maximum output current load resistance load capacitance note 3 (THD + N)/S < 0.1%; RL = 800 with respect to VSSA 0.45VDDA - - 3 - 0.55VDDA - - - 50 V k mA k pF HIGH-level input voltage LOW-level input voltage input leakage current input capacitance at 2.0 V supply voltage at 3.0 V supply voltage at 2.0 V supply voltage at 3.0 V supply voltage
-0.5 -0.5 - - 0.9VDDD 0.4VDDD -0.5
3-level input: pin PCS HIGH-level input voltage MID-level input voltage LOW-level input voltage VDDD + 0.5 0.6VDDD +0.5 V V V
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
14 AC CHARACTERISTICS
UDA1334BT
14.1 2.0 V supply voltage VDDD = VDDA = 2.0 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k.; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL DAC Vo(rms) Vo output voltage (RMS value) unbalance between channels at 0 dB (FS) digital input - - - - - - - - fripple = 1 kHz; Vripple = 30 mV (p-p) - 600 0.1 -80 -37 -75 -35 97 95 100 60 - - - - - - - - - - mV dB dB dB dB dB dB dB dB dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
(THD + N)/S total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal fs = 44.1 kHz; at -60 dB; ratio A-weighted fs = 96 kHz; at 0 dB fs = 96 kHz; at -60 dB; A-weighted S/N cs PSRR signal-to-noise ratio channel separation power supply rejection ratio fs = 96 kHz; code = 0; A-weighted
fs = 44.1 kHz; code = 0; A-weighted -
14.2 3.0 V supply voltage VDDD = VDDA = 3.0 V; fi = 1 kHz; Tamb = 25 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified. SYMBOL DAC Vo(rms) Vo output voltage (RMS value) unbalance between channels at 0 dB (FS) digital input - - - - - - - - fripple = 1 kHz; Vripple = 30 mV (p-p) - 900 0.1 -90 -40 -85 -37 100 98 100 60 - - - - - - - - - - mV dB dB dB dB dB dB dB dB dB PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
(THD + N)/S total harmonic fs = 44.1 kHz; at 0 dB distortion-plus-noise to signal fs = 44.1 kHz; at -60 dB; ratio A-weighted fs = 96 kHz; at 0 dB fs = 96 kHz; at -60 dB; A-weighted S/N cs PSRR signal-to-noise ratio channel separation power supply rejection ratio fs = 96 kHz; code = 0; A-weighted
fs = 44.1 kHz; code = 0; A-weighted -
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
14.3 Timing VDDD = VDDA = 1.8 to 3.6 V; Tamb = -20 to +85 C; RL = 5 k; all voltages with respect to ground (pins VSSA and VSSD); unless otherwise specified; note 1. SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing (see Fig.6) Tsys system clock cycle time fsys = 256fs fsys = 384fs fsys = 512fs tCWH tCWL Reset timing treset fBCK tBCKH tBCKL tr tf tsu(DATAI) th(DATAI) tsu(WS) th(WS) Note 1. The typical value of the timing is specified at fs = 44.1 kHz (sampling frequency). reset time 1 - 50 50 - - 20 0 20 10 - - - - - - - - - - - 64fs - - 20 20 - - - - s Hz ns ns ns ns ns ns ns ns system clock HIGH time system clock LOW time fsys < 19.2 MHz fsys 19.2 MHz fsys < 19.2 MHz fsys 19.2 MHz 35 23 17 88 59 44 780 520 390 ns ns ns
0.3Tsys - 0.4Tsys - 0.3Tsys - 0.4Tsys -
0.7Tsys ns 0.6Tsys ns 0.7Tsys ns 0.6Tsys ns
Serial interface timing (see Fig.7) bit clock frequency bit clock HIGH time bit clock LOW time rise time fall time set-up time data input hold time data input set-up time word select hold time word select
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
UDA1334BT
handbook, full pagewidth
t CWH
t CWL Tsys
MGR984
Fig.6 System clock timing.
handbook, full pagewidth
WS th(WS) tf tsu(WS)
tBCKH tr BCK tBCKL Tcy(BCK) DATAI
tsu(DATAI) th(DATAI)
MGL880
Fig.7 Serial interface timing.
2002 May 22
15
Philips Semiconductors
Product specification
Low power audio DAC
15 APPLICATION INFORMATION
UDA1334BT
handbook, full pagewidth
analog supply voltage R7 1
digital supply voltage R6 1
C9 47 F (16 V) C10 100 nF (63 V) VSSA system clock R5 47 BCK WS DATAI SFOR1 SFOR0 SYSCLK 15 6
C5 47 F (16 V) C6 100 nF (63 V)
VDDA 13 5
VSSD 4
VDDD
14 1 2 3 7 11
VOUTL C3 47 F (16 V)
R3 100 R1 220 k C1 10 nF (63 V)
left output
UDA1334BT
16
VOUTR C4 47 F (16 V)
R4 100 R2 220 k C2 10 nF (63 V)
right output
MUTE DEEM PCS
8 9 10 12
Vref(DAC) C8 100 nF (63 V) C7 47 F (16 V)
MGU677
Fig.8 Typical application diagram.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
16 PACKAGE OUTLINE SO16: plastic small outline package; 16 leads; body width 3.9 mm
UDA1334BT
SOT109-1
D
E
A X
c y HE vMA
Z 16 9
Q A2 A1 pin 1 index Lp 1 e bp 8 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 10.0 9.8 E (1) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 0.039 0.016 Q 0.7 0.6 0.028 0.020 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.39 0.014 0.0075 0.38
0.244 0.041 0.228
8 0o
o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT109-1 REFERENCES IEC 076E07 JEDEC MS-012 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
2002 May 22
17
Philips Semiconductors
Product specification
Low power audio DAC
17 SOLDERING 17.1 Introduction to soldering surface mount packages
UDA1334BT
If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 17.4 Manual soldering
This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all surface mount IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. 17.2 Reflow soldering
Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. 17.3 Wave soldering
Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed.
Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
17.5 Suitability of surface mount IC packages for wave and reflow soldering methods PACKAGE(1) BGA, LBGA, LFBGA, SQFP, TFBGA, VFBGA HBCC, HBGA, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes not suitable not suitable(3)
UDA1334BT
SOLDERING METHOD WAVE REFLOW(2) suitable suitable suitable suitable suitable
suitable not not recommended(4)(5) recommended(6)
1. For more detailed information on the BGA packages refer to the "(LF)BGA Application Note" (AN01026); order a copy from your Philips Semiconductors sales office. 2. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is suitable for LQFP, TQFP and QFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
2002 May 22
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Philips Semiconductors
Product specification
Low power audio DAC
18 DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
UDA1334BT
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. 19 DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 20 DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 May 22
20
Philips Semiconductors
Product specification
Low power audio DAC
NOTES
UDA1334BT
2002 May 22
21
Philips Semiconductors
Product specification
Low power audio DAC
NOTES
UDA1334BT
2002 May 22
22
Philips Semiconductors
Product specification
Low power audio DAC
NOTES
UDA1334BT
2002 May 22
23
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/01/pp24
Date of release: 2002
May 22
Document order number:
9397 750 09744

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